Design issue analysis for InAs nanowire tunnel FETs
Identifieur interne : 003215 ( Main/Repository ); précédent : 003214; suivant : 003216Design issue analysis for InAs nanowire tunnel FETs
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Abstract
InAs nanowire-tunnel field effect transistors (NW-TFETs) are being considered for future, beyond-Si electronics. They offer the possibility of beating the ideal thermal limit to the inverse subthreshold slope of 60 mV/dec and thus promise reduced power operation. However, whether the tunneling can provide sufficient on-current for high-speed operation is an open question. In this work, for a p-i-n device, we investigate the source doping level necessary to achieve a target on-current (1 μA) while maintaining a high ION/IOFF ratio (1×106) for a range of NW diameters (2 -8 nm). With a fixed drain bias voltage and a maximum gate overdrive, we compare the performance in terms of the inverse subthreshold slope (SS) and ION/IOFF ratio as a function of NW-diameter and source doping. As expected, increasing the source doping level increases the current as a result of the reduced screening length and increased electric field at source which narrows the tunnel barrier. However, since the degeneracy is also increasing, it moves the effective energy window for tunneling away from the barrier where it is the narrowest. This, in turn, tends to decrease the current for a given voltage which, along with the consideration of inverse SS and ION/IOFF ratio leads to an optimum choice of source doping.
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<record><TEI><teiHeader><fileDesc><titleStmt><title xml:lang="en" level="a">Design issue analysis for InAs nanowire tunnel FETs</title><author><name sortKey="Sarwat Sylvia, Somaia" uniqKey="Sarwat Sylvia S">Somaia Sarwat Sylvia</name><affiliation wicri:level="1"><inist:fA14 i1="01"><s1>Department of Electrical Engineering, University of California</s1><s2>Riverside, California 92521-0204</s2><s3>USA</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ><sZ>4 aut.</sZ></inist:fA14><country>États-Unis</country><wicri:noRegion>Riverside, California 92521-0204</wicri:noRegion></affiliation></author><author><name sortKey="Abul Khayer, M" uniqKey="Abul Khayer M">M. Abul Khayer</name><affiliation wicri:level="1"><inist:fA14 i1="01"><s1>Department of Electrical Engineering, University of California</s1><s2>Riverside, California 92521-0204</s2><s3>USA</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ><sZ>4 aut.</sZ></inist:fA14><country>États-Unis</country><wicri:noRegion>Riverside, California 92521-0204</wicri:noRegion></affiliation><affiliation wicri:level="1"><inist:fA14 i1="02"><s1>Intel Corporation</s1><s3>USA</s3><sZ>2 aut.</sZ></inist:fA14><country>États-Unis</country><wicri:noRegion>Intel Corporation</wicri:noRegion></affiliation></author><author><name sortKey="Alam, Khairul" uniqKey="Alam K">Khairul Alam</name><affiliation wicri:level="1"><inist:fA14 i1="03"><s1>East West University</s1><s2>Dhaka</s2><s3>BGD</s3><sZ>3 aut.</sZ></inist:fA14><country>Bangladesh</country><wicri:noRegion>East West University</wicri:noRegion></affiliation></author><author><name sortKey="Lake, Roger K" uniqKey="Lake R">Roger K. Lake</name><affiliation wicri:level="1"><inist:fA14 i1="01"><s1>Department of Electrical Engineering, University of California</s1><s2>Riverside, California 92521-0204</s2><s3>USA</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ><sZ>4 aut.</sZ></inist:fA14><country>États-Unis</country><wicri:noRegion>Riverside, California 92521-0204</wicri:noRegion></affiliation></author></titleStmt><publicationStmt><idno type="inist">12-0132310</idno><date when="2011">2011</date><idno type="stanalyst">PASCAL 12-0132310 INIST</idno><idno type="RBID">Pascal:12-0132310</idno><idno type="wicri:Area/Main/Corpus">002026</idno><idno type="wicri:Area/Main/Repository">003215</idno></publicationStmt><seriesStmt><idno type="ISSN">0277-786X</idno><title level="j" type="abbreviated">Proc. SPIE Int. Soc. Opt. Eng.</title><title level="j" type="main">Proceedings of SPIE, the International Society for Optical Engineering</title></seriesStmt></fileDesc><profileDesc><textClass><keywords scheme="KwdEn" xml:lang="en"><term>Binary compound</term><term>Electric field</term><term>Field effect transistor</term><term>High speed</term><term>Indium Arsenides</term><term>Nanotechnology</term><term>Nanowires</term><term>Performance evaluation</term><term>Tunnel effect</term></keywords><keywords scheme="Pascal" xml:lang="fr"><term>Effet tunnel</term><term>Champ électrique</term><term>Nanotechnologie</term><term>Grande vitesse</term><term>Composé binaire</term><term>Indium Arséniure</term><term>Nanofil</term><term>Transistor effet champ</term><term>Evaluation performance</term><term>InAs</term><term>As In</term><term>8530T</term><term>0130C</term></keywords><keywords scheme="Wicri" type="concept" xml:lang="fr"><term>Nanotechnologie</term></keywords></textClass></profileDesc></teiHeader><front><div type="abstract" xml:lang="en">InAs nanowire-tunnel field effect transistors (NW-TFETs) are being considered for future, beyond-Si electronics. They offer the possibility of beating the ideal thermal limit to the inverse subthreshold slope of 60 mV/dec and thus promise reduced power operation. However, whether the tunneling can provide sufficient on-current for high-speed operation is an open question. In this work, for a p-i-n device, we investigate the source doping level necessary to achieve a target on-current (1 μA) while maintaining a high I<sub>ON</sub>/I<sub>OFF</sub> ratio (1×10<sup>6</sup>) for a range of NW diameters (2 -8 nm). With a fixed drain bias voltage and a maximum gate overdrive, we compare the performance in terms of the inverse subthreshold slope (SS) and I<sub>ON</sub>/I<sub>OFF</sub> ratio as a function of NW-diameter and source doping. As expected, increasing the source doping level increases the current as a result of the reduced screening length and increased electric field at source which narrows the tunnel barrier. However, since the degeneracy is also increasing, it moves the effective energy window for tunneling away from the barrier where it is the narrowest. This, in turn, tends to decrease the current for a given voltage which, along with the consideration of inverse SS and I<sub>ON</sub>/I<sub>OFF</sub> ratio leads to an optimum choice of source doping.</div></front></TEI><inist><standard h6="B"><pA><fA01 i1="01" i2="1"><s0>0277-786X</s0></fA01><fA02 i1="01"><s0>PSISDG</s0></fA02><fA03 i2="1"><s0>Proc. SPIE Int. Soc. Opt. Eng.</s0></fA03><fA05><s2>8102</s2></fA05><fA08 i1="01" i2="1" l="ENG"><s1>Design issue analysis for InAs nanowire tunnel FETs</s1></fA08><fA09 i1="01" i2="1" l="ENG"><s1>Nanoengineering : fabrication, properties, optics, and devices VIII</s1></fA09><fA11 i1="01" i2="1"><s1>SARWAT SYLVIA (Somaia)</s1></fA11><fA11 i1="02" i2="1"><s1>ABUL KHAYER (M.)</s1></fA11><fA11 i1="03" i2="1"><s1>ALAM (Khairul)</s1></fA11><fA11 i1="04" i2="1"><s1>LAKE (Roger K.)</s1></fA11><fA12 i1="01" i2="1"><s1>DOBISZ (Elizabeth Ann)</s1><s9>ed.</s9></fA12><fA12 i1="02" i2="1"><s1>ELDADA (Louay A.)</s1><s9>ed.</s9></fA12><fA14 i1="01"><s1>Department of Electrical Engineering, University of California</s1><s2>Riverside, California 92521-0204</s2><s3>USA</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ><sZ>4 aut.</sZ></fA14><fA14 i1="02"><s1>Intel Corporation</s1><s3>USA</s3><sZ>2 aut.</sZ></fA14><fA14 i1="03"><s1>East West University</s1><s2>Dhaka</s2><s3>BGD</s3><sZ>3 aut.</sZ></fA14><fA18 i1="01" i2="1"><s1>SPIE</s1><s3>USA</s3><s9>org-cong.</s9></fA18><fA18 i1="02" i2="1"><s1>Air Live</s1><s3>INC</s3><s9>org-cong.</s9></fA18><fA18 i1="03" i2="1"><s1>Fruhmann GmbH</s1><s3>INC</s3><s9>org-cong.</s9></fA18><fA20><s2>81020O.1-81020O.6</s2></fA20><fA21><s1>2011</s1></fA21><fA23 i1="01"><s0>ENG</s0></fA23><fA25 i1="01"><s1>SPIE</s1><s2>Bellingham, Wash.</s2></fA25><fA26 i1="01"><s0>978-0-8194-8712-4</s0></fA26><fA43 i1="01"><s1>INIST</s1><s2>21760</s2><s5>354000174765660130</s5></fA43><fA44><s0>0000</s0><s1>© 2012 INIST-CNRS. All rights reserved.</s1></fA44><fA45><s0>13 ref.</s0></fA45><fA47 i1="01" i2="1"><s0>12-0132310</s0></fA47><fA60><s1>P</s1><s2>C</s2></fA60><fA61><s0>A</s0></fA61><fA64 i1="01" i2="1"><s0>Proceedings of SPIE, the International Society for Optical Engineering</s0></fA64><fA66 i1="01"><s0>USA</s0></fA66><fC01 i1="01" l="ENG"><s0>InAs nanowire-tunnel field effect transistors (NW-TFETs) are being considered for future, beyond-Si electronics. They offer the possibility of beating the ideal thermal limit to the inverse subthreshold slope of 60 mV/dec and thus promise reduced power operation. However, whether the tunneling can provide sufficient on-current for high-speed operation is an open question. In this work, for a p-i-n device, we investigate the source doping level necessary to achieve a target on-current (1 μA) while maintaining a high I<sub>ON</sub>/I<sub>OFF</sub> ratio (1×10<sup>6</sup>) for a range of NW diameters (2 -8 nm). With a fixed drain bias voltage and a maximum gate overdrive, we compare the performance in terms of the inverse subthreshold slope (SS) and I<sub>ON</sub>/I<sub>OFF</sub> ratio as a function of NW-diameter and source doping. As expected, increasing the source doping level increases the current as a result of the reduced screening length and increased electric field at source which narrows the tunnel barrier. However, since the degeneracy is also increasing, it moves the effective energy window for tunneling away from the barrier where it is the narrowest. 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Conference</s1><s2>08</s2><s3>San Diego CA USA</s3><s4>2011-08-23</s4></fA30></pR></standard></inist></record>Pour manipuler ce document sous Unix (Dilib)
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